Actel Libero IDE Platinum v.8.5 FPGA Product Design Platinum Edition
ISO | 1.17 GB | 5% recovery
ISO | 1.17 GB | 5% recovery
Libero Integrated Design Environment (IDE) Platinum Edition
In order to expand its industry-leading chip-scale-specific and system-level power-saving solutions, Actel has announced the launch of a new version of Libero Integrated Design Environment (IDE), with important new features include power-driven layout, and allows designers to further optimize design, and reduce the typical design of dynamic power consumption up to 30%. By Libero's SmartPower tool built into the advanced power analysis capabilities, the enhanced analysis of the environment will be the first time allow users to design all the features of mode-depth understanding of their power applications. In addition, the portable product designers can make use of its innovative battery life evaluation function, with its FPGA design power curve based on accurate calculation of battery life - this is the first time in the field can be made available for Gate Array (FPGA) design realize the function of tools.
Actel vice president of software engineering, Jim Davis, said: "Although the entire electronics industry in the provision of high efficacy of chips and systems have made progress, Actel solutions for low-power applications is no doubt laid the standards. Libero IDE v8 by adding advanced layout optimization and power analysis capabilities, designers can more effectively achieve the lowest power solution. "
New version of Libero IDE support for all Actel low-power product line, including ultra-low power IGLOO FPGA and mixed-signal Actel Fusion Programmable System-on-chip (PSC).
Power-driven layout capabilities to reduce dynamic power consumption up to 30%
The new Libero IDE is a new option in active play SmartPower for power-driven layout design and analysis of data, so that designers can reduce the negative capacitive CD, rapid realize dynamic power savings. IGLOO device to reduce power consumption to an average of 13 percent, and some designs can reduce power consumption up to 30%.
Battery life evaluation function for battery-powered portable product design staff to provide assistance
In the Libero IDE v8 in, SmartPower features designed to provide the ability to create a power curve to help estimate the required power and battery requirements. Power curve by the user defined FPGA functionality mode or in custom combinations the percentage of time, such as activities, standby or Flash * Freeze mode. For example, in order to provide portable or handheld designed to assess battery life, the user can input the necessary battery capacity and current FPGA power curve, SmartPower will show that the expected battery life, as well as the target FPGA-based real power curve of the actual accuracy power consumption of the report.
Enhanced SmartPower analysis capabilities designed to realize a portable high-efficacy
Libero IDE v8. Also enhanced SmartPower features, to analyze the entire FPGA and the device or design a specific part of the power consumption, such as time-domain, switching cycle, as well as the pseudo-conversion (spurious transition), and these factors will increase the device's overall individual power consumption. For example, a cycle accurate power analysis option allows designers to view each clock cycle of the peak power consumption, as well as the entire simulation process, the average power consumption.
SmartPower analysis tool switch options to determine the increase in power consumption caused by "dangerous", or pseudo-conversion conditions, allows users to identify these issues and make amendments, thereby reducing power consumption. In a typical design, a dangerous condition to occupy about 20% of power consumption. In some circuits, such as the combination of adder logic, pseudo-conversion power consumption caused by the possibility of up to 70% of the overall power consumption.
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