SynaptiCAD Product Suite 13.30a

SynaptiCAD Product Suite 13.30a | 84,4 MB
TestBencher Pro generates reactive VHDL, Verilog, OpenVera, e, and TestBuilder test benches and bus-functional models from language-independent timing diagrams. The generated test benches are capable of applying different stimulus vectors depending on simulation response so that the test bench functions as a behavioral model of the environment in which the system being tested will operate. TestBencher Pro is an excellent tool for testing large FPGA and ASIC designs.

BugHunter Pro is a graphical debugging system for Verilog, VHDL, and C++ simulators. BugHunter supports all major HDL simulators. Tool features include single step debugging, unit-level test bench generation, streaming of waveform data, project management, syntax highlighting editor, and a hierarchy tree for navigating the user's design. The unit-level test bench generation is unique in that it lets a user draw stimulus waveforms and then auto-generates, compiles, and runs the stimulus model and wrapper code. It is one of the fastest ways to test a model and make sure that everything is working correctly.
VeriLogger Pro is a new type of Verilog simulation environment that combines all the features of a traditional Verilog simulator with the most powerful graphical test vector generator on the planet. Model testing is so fast in VeriLogger Pro that you can perform true bottom-up testing of every model in your design, a critical step often skipped in the race to market.
WaveFormer Pro combines a timing diagram editor, a stimulus generator, and an interactive HDL simulator to form a groundbreaking EDA tool that should be in every digital designer’s tool kit. WaveFormer Pro allows you to automatically generate and simulate timing diagrams using common Boolean and registered logic equations. WaveFormer Pro can also import or export waveforms to VHDL, Verilog, Tektronix, HP and Agilent's logic analyzers & pattern generators, SPICE, ABEL, and a variety of gate level simulators.
SimuTAG is a functional and real time verification system for FPGAs. Quickly find logic and synthesis errors by comparing FPGA functional results against RTL model simulation results. Validate real time FPGA results using Verilog and VHDL test benches.
SimuTAG is a functional and real time verification system for FPGAs. Quickly find logic and synthesis errors by comparing FPGA functional results against RTL model simulation results. Validate real time FPGA results using Verilog and VHDL test benches.
DataSheet Pro DataSheet Pro provides documentation professionals with a more efficient environment for the management of documents containing multiple timing diagrams. Features include Object Linking and Embedding (OLE) to provide immediate in-place editing of timing diagrams, style sheet support, image view support, web-ready image generation, project management, and support for the industry-standard Timing Diagram Markup Language (TDML) format.
For the budget conscious engineer, we provide Timing Diagrammer Pro, a powerful, feature-laden timing diagram editor with an unbeatable price. Analyze your design in the early stages, before you have a schematic. Perform true full-range min/max timing analysis to eliminate all timing violations and race conditions. Timing Diagrammer Pro automatically calculates critical paths and adjusts for reconvergent fanout. Inserting diagrams into word processors is painless, thanks to a variety of image capture formats.
Gigawave viewer combines SynaptiCAD's WaveViewer with our high-performance gigawave compression engine to create the lowest cost waveform viewer capable of handling multi-gigabyte VCD files. GigaWave also loads SPICE results, TDML, logic analyzer data, and more.

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